1. Field of the Invention
The present invention relates to a two-input two-output differential latch circuit for use in analog-to-digital converters and the like.
2. Description of the Background Art
Conventionally, analog-to-digital converters (referred to hereinafter as A-D converters) contain a voltage comparator for comparing two signal voltages to output a logic signal "H" or "L". FIG. 10 is a circuit diagram of a conventional differential latch circuit in a voltage comparator which is disclosed in "Analog MOS Integrated Circuit FOR SIGNAL PROCESSING", p. 434, FIG. 6.25.
In FIG. 10, the reference numeral 1 designates a power supply voltage (referred to hereinafter as Vdd); 2 designates a ground voltage (referred to hereinafter as Vss; specifically 0 V); 3 and 4 designate p-channel MOS transistors (referred to hereinafter as PMOS transistors) each having a source terminal connected to the Vdd 1 and functioning as an active load resistor; and 5 through 11 designate n-channel MOS transistors (referred to hereinafter as NMOS transistors). The reference character a and b designate input terminals receiving input signals; c and d designate output terminals for providing logic signals; and A and B designate nodes connected to the output terminals c and d, respectively.
At the node A, the drain terminals of the PMOS transistor 3 and NMOS transistors 5, 7, and the gate electrode of the NMOS transistor 8 are connected together. At the node B, the drain terminals of the PMOS transistor 4 and NMOS transistors 6, 8, and the gate electrode of the NMOS transistor 7 are connected together. The source terminals of the NMOS transistors 5, 6 are commonly connected to the drain terminal of the NMOS transistor 9, and the source terminals of the NMOS transistors 7, 8 are commonly connected to the drain terminal of the NMOS transistor 10. The reference character C designates a node connecting the NMOS transistors 5, 6 and 9, and D designates a node connecting the NMOS transistors 7, 8 and 10. The NMOS transistor 11 has a source terminal connected to the Vss 9 and a drain terminal connected to the source terminals of the NMOS transistors 9, 10. The reference character E designates a node connecting the NMOS transistors 9, 10 and 11.
The input terminals a and b are connected to the gate electrodes of the NMOS transistors 5 and 6, respectively.
The reference characters Vin1 and Vin2 designate the potentials of the input signals applied to the input terminals a and b, respectively; Vout1 and Vout2 designate the potentials of the output signals outputted from the output terminal c and d, respectively; Biasl designates a bias voltage applied to the gate electrode of the NMOS transistor 11 to operate the NMOS transistor 11 as a constant current source in a saturation region; Bias2 designates a bias voltage commonly applied to the gate electrodes of the PMOS transistors 3, 4 to operate the PMOS transistors 3, 4 as active load resistors in the saturation region.
The reference characters X and X designate complementary digital signals applied to the gate electrodes of the NMOS transistors 9 and 10, respectively, for controlling the switching between a through mode and a latch mode of the differential latch circuit. The NMOS transistors 9, 10 serve as switches, and the H level of the signals X and X is set to a potential which operates the NMOS transistors 9, 10 when conducting in a linear region.
The operation of the differential latch circuit will be described below.
The differential latch circuit is in the through mode when X=H and X=L, and is in the latch mode when X=L and X=H. The two modes are alternately repeated at predetermined time intervals.
(1) X=H and X=L (through mode)
The NMOS transistor 9 is ON and the NMOS transistor 10 is OFF. The entire current produced by the NMOS transistor 11 passes through the NMOS transistor 9. Thus the NMOS transistors 5, 6, 11 and PMOS transistors 3, 4 form a conventional differential amplifier circuit which outputs the output potentials Vout1 and Vout2 having a potential difference based on the potential difference between the input potentials Vin1 and Vin2.
(2) X=L and X=H (latch mode)
Conversely, the NMOS transistor 9 is OFF and the NMOS transistor 10 is ON. The entire current produced by the NMOS transistor 11 passes through the NMOS transistor 10, and the above noted differential amplifier circuit does not function.
When Vin1&gt;Vin2 in the through mode immediately prior to the start of the latch mode, the output potentials Vout1 and Vout2 are set so that the potential difference satisfies Vout1&lt;Vout2. Upon switching to the latch mode, the output potential Vout1 is the gate voltage of the NMOS transistor 8 and the output potential Vout2 is the gate voltage of the NMOS transistor 7. Then the drain current of the NMOS transistor 7 is greater than the drain current of the NMOS transistor 8. This further decreases the output potential Vout1 which is the drain potential of the NMOS transistor 7 and further increases the output potential rout: which is the drain potential of the NMOS transistor 8, The interaction such that the increase in output potential Vout2 accelerates the decrease in output potential Vout1 and vice versa determines Vout1=L and Vout2=H. When Vin1&lt;Vin2 immediately prior to the start of the latch mode, the inverted operation is performed to determine Vout1=H and Vout2=L.
FIG. 11 is a circuit diagram of a voltage comparator using the differential latch circuit of FIG. 10. The reference numerals 12 and 13 designate differential amplifiers of the same construction; and 14 designates the differential latch circuit of FIG. 10.
FIG. 12 is a circuit diagram of the differential amplifiers 12 and 13 each includes an NMOS transistor 15 serving as a constant current source, NMOS transistors 16 and 17 having source terminals connected to the drain terminal of the NMOS transistor 15, a PMOS transistor 18 having a drain terminal connected to the drain terminal of the NMOS transistor 16, and a PMOS transistor 19 having a drain terminal connected to the drain terminal of the NMOS transistor 17. Each of the differential amplifiers 12 and 13 has input terminals a and b connected respectively to the gate electrodes of the NMOS transistors 16 and 17, and output terminals c and d connected respectively to the drain terminals of the NMOS transistors 16 and 17, and amplifies a potential difference between Vin1 and Vin2 of the signals received at the input terminals a and b into a potential difference between Vout1 and Vout2 at the output terminals c and d. The reference character Bias02 designates a bias voltage applied to the gate electrodes of the PMOS transistors 18 and 19 to operate the PMOS transistors 18 and 19 as active load resistors; and Bias01 designates a bias voltage applied to the gate electrode of the NMOS transistor 15 to operate the NMOS transistor 15 as a constant current source.
Referring to FIG. 11, the output terminals c and d of the differential amplifier 12 are connected respectively to the input terminals a and b of the differential amplifier 13, and the output terminals c and d of the differential amplifier 13 are connected respectively to the input terminals a and b of the differential latch circuit 14. The bias voltages Bias01 and Bias02 are commonly applied to the differential amplifiers 12 and 13.
For example, when an analog signal voltage Vin is applied to the input terminal a of the differential amplifier 12 and a constant reference voltage Vref for comparison is applied to the input terminal b thereof, the differential amplifiers 12 and 13 amplify the voltage difference between Vin and Vref, and the differential amplifier 13 outputs two output voltages which are input voltages to the differential latch circuit 14. The differential latch circuit 14 alternately repeats the through mode and latch mode with time to further amplify the potential difference in the through mode and determine the logic signal "H" or "L" of the output signals Vout1 and Vout2 in the latch mode. In the voltage comparator circuit of FIG. 11, Vout1=H and Vout2=L in the latch mode when Vin&lt;Vref at the end of the through mode. These output signals are applied to a CMOS digital encoder at the next stage for converting the analog signal voltages to digital signals.
FIG. 13 shows another conventional differential latch circuit corresponding to a circuit arrangement comprising transistors M5 to M10 of a previous-stage comparator disclosed in "Papers for Institute of Electronics, Information and Communication Engineers of Japan, C-II, Vol. J74-C-II, No. 2, February 1994", pp. 81-91, FIG. 4 on page 84.
In FIG. 13, the reference numerals 71 and 72 designate PMOS transistors; and 73 and 74 designate NMOS transistors. The PMOS transistor 71 and NMOS transistor 73 have drain terminals connected together and gate electrodes connected together. The reference character G I designates a connection node between the drain terminals of the PMOS transistor 71 and NMOS transistor 73, and H1 designates a connection node between the gate electrodes thereof. Similarly, the PMOS transistor 72 and NMOS transistor 74 have drain terminals connected together, and gate electrodes connected together. The reference character G2 designates a connection node between the drain terminals of the PMOS transistor 72 and NMOS transistor 74, and H2 designates a connection node between the gate electrodes thereof.
The reference numerals 75 through 78 designate switch circuits. An input terminal a is connected to the nodes G1 and H2 through the switch circuit 75, and an input terminal b is connected to the nodes H1 and G2 through the switch circuit 76. An output terminal c is connected to the nodes G1 and H2, and an output terminal d is connected to the nodes G2 and H1. The Vdd 1 is connected to the source terminals of the PMOS transistors 71 and 72 through the switch circuit 77, and the Vss 2 is connected to the source terminals of the NMOS transistors 73 and 74 through the switch circuit 78.
The reference character X designates a digital signal applied to the switch circuits 75 and 76, and X designates a digital signal applied to the switch circuits 77 and 78. The signals X and X are complementary digital signals. Each of the switch circuits 75 to 78 is ON when the applied digital signal is "H" and is OFF when it is "L". Thus, the switch circuits 77 and 78 are OFF when the switch circuits 75 and 76 are ON, and the switch circuits 75 and 76 are OFF when the switch circuits 77 and 78 are ON. Other reference numerals and characters of FIG. 13 designate parts identical with or corresponding to those of FIG. 10.
The operation of the differential latch circuit will be described with reference to the timing chart of FIG. 14. FIG. 14 shows variations in output potentials Vout1 and Vout2 versus time.
The differential latch circuit, similar to that of FIG. 10, is in the through mode when X=H and X=L and is in the latch mode when X=L and X=H. These two modes are alternately repeated at predetermined time intervals. It is assumed that the input signals have constant potentials Vin1 and Vin2 (Vin1&gt;Vin2).
(1) X=H and X=L (through mode)
The switch circuits 75 and 76 are ON, and the switch circuits 77 and 78 are OFF. The input terminals a and b are directly connected to the output terminals c and d, and the input signals Vin1 and Vin2 are, as they are, the output signals Vout1 and Vout2 as shown in FIG. 14. The Vdd 1 and Vss 2 are disconnected from the PMOS transistors 71, 72 and NMOS transistors 73, 74, resulting in occurrence of no latch operation.
(2) X=L and X=H (latch mode)
The switch circuits 75 and 76 are OFF, and the switch circuits 77 and 78 are ON. The Vdd 1 and Vss 2 are connected to the PMOS transistors 71, 72 and NMOS transistors 73, 74. The PMOS transistor 71 and NMOS transistor 73 form an inverter, and the PMOS transistor 72 and NMOS transistor 74 form an inverter. The output from one of the inverters is the input to the other inverter. Thus the output terminals c and d are forced to "H" or "L" using the potentials Vout1 (=Vin1) and Vout2 (=Vin2) outputted in the through mode as initial voltages.
The differential latch circuit has an inherent threshold voltage which determines "H" or "L" at its output. The threshold voltage is determined by the characteristics of the two inverters. When both of the input signal potentials Vin1 and Vin2 are higher than the threshold voltage in the through mode as shown in FIG. 14, an output voltage conflict occurs after the switching to the latch mode, that is, both of the two inverters output "L", decreasing the output signal potentials Vout1 and Vout2 to about the threshold voltage. As the output signal potential Vout2 becomes lower than the threshold voltage, the output signal potential Vout1 rises to "H" (Vdd), and the output signal potential Vout2 falls to "L" (Vss).
Referring again to FIG. 11, the differential latch circuit of FIG. 13 is used as the differential latch circuit 14, and the output terminals c and d of the differential amplifier circuit 13 are connected respectively to the input terminals a and b of the differential latch circuit of FIG. 13, thereby forming a voltage comparator.
In the differential latch circuit of FIG. 10, the NMOS transistor 9 serving as a switch is connected between the source terminals of the NMOS transistors 5, 6 receiving the input signals and the drain terminal of the NMOS transistor 11 serving as a constant current source. Unfortunately, when the NMOS transistor 9 is ON (that is, in the through mode), a voltage drop in the NMOS transistor 9 decreases the voltage applied to the drain terminal of the NMOS transistor 11. The NMOS transistor 11 having a smaller drain-source potential difference operates in the linear region, which might cause a loss of constant current property of the NMOS transistor 11 which is to serve as a current source. The result is differential amplification with unsatisfactory gain in response to the two signal inputs Vin1 and Vin2.
This prevents the differential latch circuit of FIG. 10 from amplifying the applied signals amplified by the differential amplifiers 12 and 13 as shown in FIG. 11 up to a predetermined value in the through mode. The differential latch circuit might fail to perform correct and rapid latch operation upon switching to the latch mode.
When the differential latch circuit makes a transition from the through mode to the latch mode, one of the output signal potentials Vout1 and Vout2 exhibits "L". For example, when the output signal potential Vout1 is "L", electrons are extracted from. the node A receiving the output signal potential Vout1 through the NMOS transistor 7 to the ground. However, the NMOS transistor 11 functioning as a constant current source in the saturation region has a very high ON-state resistance which generates a large potential difference. Therefore, the output signal potential Vout1 is not sufficiently lowered to the ground potential to cause a circuit at the next stage not to recognize the potential as "L" and not to operate.
The differential latch circuit of FIG. 13 normally receives the signals differentially amplified by the differential amplifiers 12 and 13 as shown in FIG. 11. At this time, the input signal potentials Vin1 and Vin2 are often deviated greatly from the threshold voltage of the differential latch circuit. As shown in FIG. 14, after the transition from the through mode to the latch mode, the output signal potentials Vout1 and Vout2 temporarily fall down, and require much time to determine the "H" or "L" level. Such a delay in level determination causes a delay of the time at which the circuit at the next stage starts processing the logic signals outputted from the differential latch circuit, resulting in a delay in the entire operation of the digital circuit at the next stage.